256k x 16 static ram cy7c1041bn cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-06496 rev. *a revised august 31, 2006 features ? temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive-a: ?40c to 85c ?high speed ?t aa = 15 ns ? low active power ? 1540 mw (max.) ? low cmos standby power (l version) ? 2.75 mw (max.) ? 2.0v data retention (400 w at 2.0v retention) ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features ? available in pb-free and non pb-free 44-pin tsop ii and molded 44-pin (400-mil) soj packages functional description the cy7c1041bn is a high-performance cmos static ram organized as 262,144 words by 16 bits. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the location specified on the address pins (a 0 through a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 17 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1041bn is available in a standard 44-pin 400-mil-wide body width soj and 44-pin tsop ii package with center power and ground (revolutionary) pinout. 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 256k x 16 array a 0 a 11 a 13 a 12 a a a 16 a 17 a 9 a 10 i/o 0 ?i/o 7 oe i/o 8 ?i/o 15 ce we ble bhe we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 top view soj 12 13 41 44 43 42 16 15 29 30 v cc a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 3 a 4 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 16 a 15 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 14 a 13 a 12 a 11 a 9 a 10 nc tsop ii [+] feedback [+] feedback
cy7c1041bn document #: 001-06496 rev. *a page 2 of 10 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v cc to relative gnd [1] .... ?0.5v to +7.0v dc voltage applied to outputs in high z state [1] ....................................?0.5v to v cc + 0.5v dc input voltage [1] ................................ ?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma selection guide -15 -20 unit maximum access time 15 20 ns maximum operating current commercial 190 170 ma industrial 210 190 automotive-a 190 maximum cmos standby current commercial 3 3 ma commercial l0.5 0.5 industrial 6 6 automotive-a 6 operating range range ambient temperature [2] v cc commercial 0c to +70c 5v 0.5 industrial ?40c to +85c automotive-a ?40c to +85c electrical characteristics over the operating range parameter description test conditions -15 -20 min. max. min. max. unit v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 v v ih input high voltage 2.2 v cc + 0.5 2.2 v cc + 0.5 v v il input low voltage [1] ?0.5 0.8 ?0.5 0.8 v i ix input load current gnd < v i < v cc ?1 +1 ?1 +1 ma i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ?1 +1 ma i cc v cc operating supply current v cc = max., f = f max = 1/t rc comm?l 190 170 ma ind?l 210 190 ma auto-a 190 ma i sb1 automatic ce power-down current?ttl inputs max. v cc , ce > v ih, v in > v ih or v in < v il , f = f max 40 40 ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 comm?l 3 3 ma comm?l l 0.5 0.5 ma ind?l 6 6 ma auto-a 6 ma notes: 1. v il (min.) = ?2.0v for pulse durations of less than 20 ns. 2. t a is the case temperature. 3. tested initially and after any design or process changes that may affect these parameters. [+] feedback [+] feedback
cy7c1041bn document #: 001-06496 rev. *a page 3 of 10 capacitance [3] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = 5.0v 8pf c out i/o capacitance 8 pf ac test loads and waveforms switching characteristics [4] over the operating range -15 -20 parameter description min. max. min. max. unit read cycle t power v cc (typical) to the first access [5] 11 s t rc read cycle time 15 20 ns t aa address to data valid 15 20 ns t oha data hold from address change 3 3 ns t ace ce low to data valid 15 20 ns t doe oe low to data valid 7 8 ns t lzoe oe low to low z 0 0 ns t hzoe oe high to high z [6, 7] 78ns t lzce ce low to low z [7] 33ns t hzce ce high to high z [6, 7] 78ns t pu ce low to power-up 0 0 ns t pd ce high to power-down 15 20 ns t dbe byte enable to data valid 7 8 ns t lzbe byte enable to low z 0 0 ns t hzbe byte disable to high z 7 8 ns notes: 4. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v, and output loading of the specified i ol /i oh and 30-pf load capacitance. 5. this part has a voltage regulator which steps down the voltage from 5v to 3.3v internally. t power time has to be provided initially before a read/write operation is started. 6. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (b) of ac test loads. transition is measured 500 mv from steady-stat e voltage. 7. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 90% 10% 3.0v gnd 90% 10% all input pulses 5v output 30 pf including jig and scope 5v output 5 pf including jig and scope (a) (b) 3 ns 3 ns output r1 481 ? r1 481 ? r2 255 ? r2 255 ? 167 ? equivalent to: venin equivalent 1.73v th [+] feedback [+] feedback
cy7c1041bn document #: 001-06496 rev. *a page 4 of 10 write cycle [8, 9] t wc write cycle time 15 20 ns t sce ce low to write end 12 13 ns t aw address set-up to write end 12 13 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 12 13 ns t sd data set-up to write end 8 9 ns t hd data hold from write end 0 0 ns t lzwe we high to low z [7] 33ns t hzwe we low to high z [6, 7] 78ns t bw byte enable to end of write 12 13 ns data retention characteristics over the operating range (l version only) parameter description conditions [11] min. max. unit v dr v cc for data retention 2.0 v i ccdr data retention current v cc = v dr = 2.0v, ce > v cc ? 0.3v, v in > v cc ? 0.3v or v in < 0.3v 200 a t cdr [3] chip deselect to data retention time 0 ns t r [10] operation recovery time t rc ns switching characteristics [4] over the operating range (continued) -15 -20 parameter description min. max. min. max. unit data retention waveform notes: 8. the internal write time of the memory is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd . 10. t r < 3 ns for the -15 speed. t r < 5 ns for the -20 and slower speeds. 11. no input may exceed v cc + 0.5v. 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce v cc [+] feedback [+] feedback
cy7c1041bn document #: 001-06496 rev. *a page 5 of 10 switching waveforms read cycle no. 1 [12, 13] read cycle no. 2 (oe controlled) [13, 14] notes: 12. device is continuously selected. oe , ce , bhe , and/or bhe = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. previous data valid data valid t rc t aa t oha address data out 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble current [+] feedback [+] feedback
cy7c1041bn document #: 001-06496 rev. *a page 6 of 10 write cycle no. 1 (ce controlled) [15, 16] write cycle no. 2 (ble or bhe controlled) notes: 15. data i/o is high impedance if oe or bhe and/or ble = v ih . 16. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we bhe, ble t t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o address bhe ,ble we ce [+] feedback [+] feedback
cy7c1041bn document #: 001-06496 rev. *a page 7 of 10 write cycle no. 3 (we controlled, oe low) truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high z high z power down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high z read lower bits only active (i cc ) l l h h l high z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high z write lower bits only active (i cc ) l x l h l high z data in write upper bits only active (i cc ) l h h x x high z high z selected, outputs disabled active (i cc ) switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe [+] feedback [+] feedback
cy7c1041bn document #: 001-06496 rev. *a page 8 of 10 ordering information speed (ns) ordering code package name package type operating range 15 cy7c1041bn-15vc 51-85082 44-pin (400-mil) molded soj commercial cy7c1041bn-15vxc 44-pin (400-mil) molded soj (pb-free) cy7c1041bn-15zc 51-85087 44-pin tsop type ii cy7c1041bn-15zxc 44-pin tsop type ii (pb-free) cy7c1041bnl-15zc 44-pin tsop type ii cy7c1041bnl-15zxc 44-pin tsop type ii (pb-free) cy7c1041bn-15zi 44-pin tsop type ii industrial cy7c1041bn-15zxi 44-pin tsop type ii (pb-free) cy7c1041bn-15vi 51-85082 44-pin (400-mil) molded soj cy7c1041bn-15vxi 44-pin (400-mil) molded soj (pb-free) 20 CY7C1041BN-20VXC 44-pin (400-mil) molded soj (pb-free) commercial cy7c1041bnl-20vxc 44-pin (400-mil) molded soj (pb-free) cy7c1041bn-20zc 51-85087 44-pin tsop type ii cy7c1041bn-20zxc 44-pin tsop type ii (pb-free) cy7c1041bn-20zi 44-pin tsop type ii industrial cy7c1041bn-20zxi 44-pin tsop type ii (pb-free) cy7c1041bn-20vxi 51-85082 44-pin (400-mil) molded soj (pb-free) cy7c1041bn-20zsxa 51-85087 44-pin tsop type ii automotive-a please contact local sales representative regarding availability of these parts. package diagrams 44-pin (400-mil) molded soj (51-85082) 51-85082-*b [+] feedback [+] feedback
cy7c1041bn document #: 001-06496 rev. *a page 9 of 10 ? cypress semiconductor corporation, 2006. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. package diagrams (continued) 44-pin tsop ii (51-85087) 51-85087-*a [+] feedback [+] feedback
cy7c1041bn document #: 001-06496 rev. *a page 10 of 10 document history page document title: cy7c1041bn 256k x 16 static ram document number: 001-06496 rev. ecn no. issue date orig. of change description of change ** 424111 see ecn nxr new data sheets *a 498575 see ecn nxr added automotive-a operating range updated ordering information table [+] feedback [+] feedback
|
